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Debugging incurs significant costs in the semiconductor industry, with some engineers spending 40% or more of their time debugging. Despite the critical importance of this skill, undergraduate students often need help to develop it. In this paper, we administered a circuit debugging test to second and third-year electrical and computer engineering (ECE) students in an introductory microelectronics class. The buggy circuit was a non-inverting amplifier printed circuit board with a misoriented op-amp. The pilot results on 26 students revealed concerns about misconceptions and biases in their debugging methodology. 54% of students focused predominantly on scrutinizing resistors, neglecting a broader exploration of potential issues. Furthermore, 46% limited their search for errors to a single potential problem, and 15% could not accurately measure resistance. Ultimately, 31% successfully identified and corrected the bug, indicating exam expectations were achievable and giving us hope that debugging skills are within reach for our students. However, specialized training may be needed to get them there. 

In the rapidly evolving world of hardware security, developing metrics for evaluating the security improvements of hardware designs is important. This work examines the prevailing threat model for secure analog-to-digital converter (ADC) architectures and explains how signal-to-noise ratio (SNR), root-mean-square error (RMSE), and bit-wise accuracy (BWA) are used to evaluate security improvements. The existing metrics are mathematically related through the proposed Proxy ADC framework. The proposed SNR-RMSE and BWA-RMSE relationships are validated using a power side-channel attack on a commercial ADC. The SNR-RMSE relationship achieves an average percent error of 1.69% across four trials, while the BWA-RMSE relationship achieves an average of 7.97%. Using results from past secure ADC works allows for additional demonstrations of the relationships. These relationships can estimate accuracy in a realistic attack scenario where ADC outputs cannot be measured to verify the evaluation, and recontextualize the metrics of standard ADC design for hardware security. Furthermore, the Proxy ADC framework allows for comparison of tradeoffs between designs’ security and efficiency, revealing trends to leverage for future secure architectures. 

This work-in-progress research-to-practice paper presents the development and pilot implementation of curriculum that introduces semiconductor contents in a high school calculus class. The demand for chips soared through the COVID-19 pandemic, exposing our country's semiconductor manufacturing and supply chain risks. The need to reassert US semiconductor leadership will require training a well-educated workforce, starting at the K-12 level. Meanwhile, K-12 STEM teachers often juggle the conflicting requirements of standardized tests and the need to cultivate 21st-century skills, deeper learning, and transferable knowledge, among others. This paper presents a pilot implementation that could address both problems. Selected teachers attended an NSF-funded Research Experience for Teachers (RET) summer program to learn about chip design basics. They also received curriculum development support to design new modules on semiconductor topics that would attract their students' interests.